| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 102 === This thesis implements the power-line communication systems with hardware components and simulates power-line communication systems with software. Compare the implementation and simulation results with each other and design the analog front-end circuit after simulation. The specification we used is G3. G3 is a physical layer specification for narrow-band power-line communication. This specification uses orthogonal frequency division multiplexing (OFDM) for data transmission and operates in the low-frequency band, from 35.9 kHz to 90.6 kHz. This thesis implements the hardware architecture of the transceiver based on G3 specification. The on-shelf hardware modules, including Xilinx Virtex-4 FPGA development board and P240 Analog Module , are used for the implementation, but the Analog Front-end is my own realization. Finally, this thesis will test the performance of the overall hardware architecture and discuss the difficulties we met while through the hardware implementation.
|
|---|
