Key Technologies of 3-D ICs for Advanced BSI-CIS Application

• Main Authors: Lyu, Dian-Rong, 呂典融
• Other Authors: Chen, Kuan-Neng
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/39417694892655714729

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Backside illumination CMOS image sensor (BSI-CIS) has many advantages such as reducing the noise beyond low illumination to lighten color distortion, enhancing the sensor current, and lowering the effect of Young's interference. Cu/Sn to Cu/Sn bump with under-fill is proposed to use in BSI-CIS fabrication. However, current Cu/Sn bump and under-fill technologies limit the scaling of the CIS chip. In this thesis, we reduce the Cu/Sn thickness successfully by novel Cu/Ni/Sn bonding and fabricate the test structure of BSI-CIS by wafer thinning and wafer bonding technologies. In addition, we evaluate the correspodning electrical characteristics and reliabilities in Kelvin test structure and daisy chain. On the other hand, during the under-fill filling, there are some issues like the micro-gap or voids between the Cu/Sn bumps. The concept of hybrid bonding can be used to solve these problems. In order to study the feasibility of hybrid bonding by Cu/Ni/Sn and polymer, we first evaluate polyimide dielectric bonding under different bonding temperature, and study the correlation between different parameters such as curing, time and temperature by FTIR. We also investigate the mechanical properties by pulling test and dicing test. These results of Cu/Ni/Sn bonding and polyimide bonding have provided the guideline for using hybrid bonding in BSI-CIS applications.