ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

• Main Authors: Fan, Mei-Lian, 范美蓮
• Other Authors: Ker, Ming-Dou
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/24460538617037423160

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === For the consideration of high integration and low cost, radio-frequency integrated circuits (RF ICs) have been fabricated in nanoscale CMOS processes. Electrostatic discharge (ESD), which has become one of the most important reliability issues in IC products, must be taken into consideration during the design phase of all IC products. Since RF ICs are very sensitive to any extra parasitic effect, ESD protection design for RF ICs in nanoscale CMOS processes needs well ESD protection ability and small parasitic effect. In this thesis, the new ESD protection design which was modified from the conventional ESD protection design without adding any extra device has proposed. The new proposed ESD protection device utilizes stacked diodes with embedded silicon-controlled rectifier (SCR) as main ESD-current-discharging paths. The optimization on layout style of the stacked diodes is more suitable for on-chip ESD protection due to its low turn-on resistance, low parasitic capacitance, and high ESD robustness. The proposed ESD protection stacked diodes with embedded SCR has been also developed for the differential low-noise amplifier (LNA). The SCR path was established directly from one differential input pad to the other differential input pad, so the pin-to-pin ESD robustness can be improved. Besides, this design had been further applied to a 24-GHz LNA in the same CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.