Study of High Speed and Low Voltage Depletion and Enhancement Mode InAs Channel HEMTs for RF and Logic Applications

• Main Author: 李宗運
• Other Authors: CHANG,EDWARD YI
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/4p3mge

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In recently years, wireless communication applications at millimeter wave band and sub-millimeter wave bands have received a lot of momentum. The applications include radar systems, cellular backbone, wireless systems, national weaponry, traffic guidance, etc. Besides, emerging millimeter wave applications such as homeland security, medical diagnosis, and high-resolution image sensor are also in development rapidly. Therefore, development of the device possessing both high frequency features and low noise characteristics is becoming urgent. High indium content InGaAs-based HEMTs are particularly promising because the excellent electrical properties of InxGa1-xAs material and the superior band-gap design of HEMT. In this study, the 60 nm InAs HEMTs processed with advanced two-step recess and Pt gate sinking technologies for RF applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 60 nm InAs HEMTs with these advanced processes exhibit better performance than the conventional InAs HEMTs at low applied voltage such as better current saturation, lower output conductance (go), smaller negative threshold-voltage (VT), higher current-gain cut-off frequency (fT) of 153 GHz and 288 GHz. The excellent electronic performances indicate the developed 60 nm InAs HEMTs are suitable for high-gain, low noise and low voltage applications. In addition to high frequency RF applications, the evaluations of 60 nm InAs HEMTs for high-speed logic applications have also been demonstrated in this study. The devices show outstanding logic performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 70 mV/V, subthreshold swing (S) is 67 mV/decade, and intrinsic gate delay (CV/ION) is less than 5.0 psec. When comparing to the mature Si technology, the InAs HEMTs exhibit smaller gate delay time. Besides, InAs HEMTs show much higher ION/IOFF performance than the most advanced InSb HEMTs. These results demonstrate that the 60 nm InAs HEMTs have great potential for future high-speed and low-voltage logic applications.