| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === Innovation of fabrication process, device, device material, and vertical channel structure benefits the mass production of CMOS devices. It continues to support and energize the performance projection of Moore’s law. Performance improvement of nanometerscaled CMOS devices requires not only overcoming a variety of fabrication challenges but also suppressing systematic variation and random effects. Except the process variation effects, the random effects including random dopants (RDs), interface traps (ITs), and work functions (WKs) are crucial for device characteristic of nanometer-scaled planar MOSFET and vertical channel field effect transistor, the bulk fin-typed field-effect-transistor.
In this thesis, we estimate the influence of RDs, ITs, and WKs using the experimentally calibrated 3D device simulation on DC characteristic of high-k/ metal gate nand p-type bulk FinFETs. One of the main findings of this thesis shows the RDF and WKF are significant among fluctuation sources. Therefore, we further study the RDF
and WKF for FinFET device. For RDF, the random position effect has been examined.
We found that the bottom of the fin is the region which is with larger energy barrier
in different aspect ratio (AR) FinFET. And this region will induce the larger fluctuation.
On the other side, we explored the random-shaped generating technique to study
the random WK-induced variability in the 16-nm FinFETs and planar MOSFET with
amorphous-based TiN/HfO2 gate stacks. This reveals that the random WKF is affected
by the random area and random location of the metal grain with different work function.
The FinFET device and structure with a minimal metal grain size can effectively reduce
characteristic fluctuation induced by the random nano-sized metal grains.
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