Implementation of a Digitally Calibrated 12-bit 25MS/s SAR ADC with an Asynchronous Clock Generator
碩士 === 國立交通大學 === 電控工程研究所 === 102 === Mismatched capacitors in the DAC due to process variations limit the resolution of a conventional capacitive SAR ADC. This thesis implemented a digitally calibrated fully differential SAR ADC. The adopted calibration scheme first estimates the real weights of th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/hcfqee |