A High-Efficiency Digitally Controlled Current-Mode DC-DC Buck Converter with Wide-Load Regulation

• Main Authors: Chao-Ying Wang, 王昭穎
• Other Authors: Muh-Tian Shiue
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/83996092170437963469

碩士 === 國立中央大學 === 電機工程學系 === 102 === For portable electronics, the extension of usage time is an essential consideration. One solution is to increase the capacity of batteries. Another solution is to reduce the power consumption, that is to say, increase the power conversion efficiency of power management IC. For the requirement of wide-load regulation, the DC-DC switching regulator is suitable to employ in portable power system. Besides, the digitally-controlled DC-DC converter offers high-degree flexibility, programmable system para- meters, scalable and reusable hardware with difference processes. System design of the digital current-mode Buck converter is based on the mathematical derivations, and verified by using behavioral models. Due to insufficient phase margin of converter power stage, a digital compensator is necessary. The digital PID controller is used to increase the phase margin of converter power stage and extend the system bandwidth. PID controller is first devised in continuous -time domain, and then converted to discrete-time domain by the bilinear transform with frequency prewarping. Phase and system bandwidth is well-mapping after transformation. There are two quant- izers ADC and DPWM in control loop, the resolutions of this two circuits are dependent on system requirements and no-limit-cycle oscillation conditions to prevent the undesirable oscillation in output voltage. Predictive current control law is employed in digital current-mode controller. Based on the information of inductor current and voltage error between feedback voltage and reference voltage, the duty cycle of PWM is accordingly adjusted to control the converter to regulate the output voltage to the desired dc level. ADC used in digital controller is based on delay-line architecture with time-to-digital conversion, the resolution is 4 bits with 10mV LSB. PID controller is realized with look-up tables to reduce area cost. DPWM uses the counter-comparator architecture to provide accurate modulation of PWM duty cycle, the resolution is 8 bits with 3.9ns time resolution. Digital current sensor based on successive-approx- imation algorithm can realize the current sensing and quantization into single procedure, resolution is 4 bits with 93.2mA LSB, sensing range is 0-1.4A. Adaptive dead-time controller with fast detection of switching node voltage is utilized to improve power conversion efficiency and prevent occurrence of shoot-through current. A monolithic on-chip soft-start circuit is used to avoid abrupt inrush current during start-up period. The proposed digitally-controlled current-mode Buck converter is implemented by 0.18-μm CMOS process with 2.66mm2 chip area. Input voltage ranges from 2.3V to 4.4V, the output voltage is 1.8V, switching frequency is 1MHz, and a wide load current range 0-1A. A 230mV voltage overshoot/und- ershoot is achieved with 26μs recovery time during 500mA load current transient. The line regulation is 9.5μV/mV, and the load regulation is 18μV/mA. The maximum power efficiency is achieved with 92%.