Allocation of Channels and Switches in Routers for Irregular On-Chip Networks

• Main Authors: Sheng-Zhi Wang, 王聖智
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/f56ana

碩士 === 國立東華大學 === 資訊工程學系 === 102 === Abstract The architecture and implementation of the interconnection network are keys to the performance of multiprocessor systems. In order to achieve better performance, low latency, high throughput, scalability and fault tolerance are essential. The interconnection network for a multiprocessor can be in either a regular topology or an irregular topology. With the interconnection network in a regular topology, routing is relatively easy to implement, but the incremental scalability and fault tolerance are poor. In comparison, for multiprocessor clusters that require scalability, the interconnection network in an irregular topology is more suitable. However, the complexity of routing algorithms for irregular networks increases. We have previously proposed a routing scheme called TRAIN (Tree-Based Routing Architecture for Irregular Networks) for regular and irregular networks used in multiprocessor clusters. Many deadlock free algorithms have been developed, but these methodologies waste link to avoid dependency cycle and require routing table on the router. TRAIN provides a way to avoid deadlock efficiently, and requires no routing tables. In this thesis, we simulate the TRAIN algorithm by using virtual channels, router speculation and other technologies. In our simulation, we modified the simulator Booksim to evaluate our routing designs in the experiments.