| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 102 === Development in the information, make sure the information correct is very
important in the transmission and storage process. Because the process of flash
memory, if access to the same block too many times, easy error occurred on the block.
To ensure that the right message can be read, error-correcting codes is very important
in the application of flash memory, which BCH code optimization. However, the
traditional serial BCH code is not good at a large number of real-time transmission of
the message, parallelizing BCH code becomes quite important.
Traditional parallel BCH decoding algorithm is used the root of generator
polynomial into the message polynomial for syndrome and use the syndrome to
calculator key equation, final use chien’s search to search the error location and
correct, this calculation very complex and long time. This paper presents an directly
algorithms to find the error location from the received message; First, create a
relationship between the information, syndrome and the error location. Using this
relationship then simplify the decoding process to the fastest parallel decoding
architecture. This paper presents an directly algorithms to find the error location from
the received message; First, create a relationship between the information, syndrome
and the error location. Using this relationship then simplify the decoding process to
achieve a better parallel decoding architecture. About benefit evaluation of decoding,
we against the number of transistor required in this decoding method and the required
number of logic gate to compare area and delay.
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