| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 102 === With the advance of integrated circuits, yield and reliability have become one of the critical and popular issues to be addressed. Error-tolerance is a novel notion that can improve yield and reliability efficiently. The research of this notion is still in progress and needs further investigation to make this notion applicable in real applications. This thesis addresses error-tolerant analysis and design issues for JPEG2000 codec. JPEG2000 is a high performance image compression standard that can outperform JPEG with higher compression ratio under the same quality. Targeting the discrete wavelet transform (DWT), inverse discrete wavelet transform (IDWT) and quantization blocks of the JPEG2000 codec, we find that error-tolerance is quite adequate to be applied to these blocks. In this thesis we implement these components and inject faults to carry out fault analysis procedures. We carefully analyze the resulting image quality produced by the faulty components using the attributes of PSNR (Peak Signal-to-Noise Ratio) and SSIM (Structural SIMilarity). The analysis results show that under the constraint of acceptable image quality, there are up to {76.7%, 78.6%, 68.4%} acceptable faults in the implemented {DWT, IDWT, quantization} blocks. Furthermore, in addition to demonstrating the error-tolerability of these blocks, the analysis results also show that the sub-circuits that contain acceptable faults can be simplified so as to reduce the area, critical path delay and power consumption. This can also be helpful to increase chip yield. By properly simplifying the target blocks while still maintaining acceptable image quality, the {area, critical path delay, power consumption} of DWT and IDWT blocks are reduced by {63.3%, 24.7%, 54.6%} and {63.4%, 27.4%, 53.2%}, respectively. The resulting image quality of DWT (IDWT) is in the range of 26.28 dB~39.91 dB (25.42 dB~40.81 dB) in terms of PSNR and 0.92~0.99 (0.93~0.99) in terms of SSIM.
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