Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

• Main Authors: Chang, Min-Sheng, 張閔盛
• Other Authors: Wang, Ting-Chi
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/18725294621657450344

碩士 === 國立清華大學 === 資訊工程學系 === 102 === Since the implementation of 3D ICs is problematic, interposer-based 3D ICs (or known as 2.5D ICs), using a silicon interposer as an interface between a package and dies, has been seen as an alternative approach to 3D ICs. In a 2.5D IC, the floorplan of dies on the interposer and the signal assignment of macro-bumps and TSVs would impact the routing wirelength. Because overlong routing wirelength would degrade the performance of 2.5D ICs and cause timing violations, the die floorplanning and signal assignment problems for 2.5D ICs are critical. In this thesis, we propose an enumeration-based floorplanning algorithm (EFA) to solve the signal-aware die floorplanning problem (SDFP), and we solve a signal assignment problem (SAP) for micro-bumps and TSVs by a min-cost max-flow (MCMF) algorithm. To speed up the EFA and the min-cost max-flow algorithm, we also present several acceleration techniques. The experimental results show that the proposed floorplanning and signal assignment algorithms are effective and the speedup is significant when the proposed acceleration techniques are used.