High Speed Read Circuit and I/O Design for 3D Stacked RRAM

碩士 === 國立清華大學 === 電子工程研究所 === 102 === 因申請專利緣故，資料延後公開

Bibliographic Details
Main Authors:	Chen, Yi-Wei, 陳翊維
Other Authors:	Chang, Meng-Fan
Format:	Others
Language:	en_US
Published:	2013
Online Access:	http://ndltd.ncl.edu.tw/handle/fqyuu2

id	ndltd-TW-102NTHU5428003
record_format	oai_dc
spelling	ndltd-TW-102NTHU54280032019-05-15T21:03:44Z http://ndltd.ncl.edu.tw/handle/fqyuu2 High Speed Read Circuit and I/O Design for 3D Stacked RRAM 三維堆疊電阻式記憶體高速讀取電路與I/O設計 Chen, Yi-Wei 陳翊維碩士國立清華大學電子工程研究所 102 因申請專利緣故，資料延後公開 Chang, Meng-Fan 張孟凡 2013 學位論文 ; thesis 68 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立清華大學 === 電子工程研究所 === 102 === 因申請專利緣故，資料延後公開
author2	Chang, Meng-Fan
author_facet	Chang, Meng-Fan Chen, Yi-Wei 陳翊維
author	Chen, Yi-Wei 陳翊維
spellingShingle	Chen, Yi-Wei 陳翊維 High Speed Read Circuit and I/O Design for 3D Stacked RRAM
author_sort	Chen, Yi-Wei
title	High Speed Read Circuit and I/O Design for 3D Stacked RRAM
title_short	High Speed Read Circuit and I/O Design for 3D Stacked RRAM
title_full	High Speed Read Circuit and I/O Design for 3D Stacked RRAM
title_fullStr	High Speed Read Circuit and I/O Design for 3D Stacked RRAM
title_full_unstemmed	High Speed Read Circuit and I/O Design for 3D Stacked RRAM
title_sort	high speed read circuit and i/o design for 3d stacked rram
publishDate	2013
url	http://ndltd.ncl.edu.tw/handle/fqyuu2
work_keys_str_mv	AT chenyiwei highspeedreadcircuitandiodesignfor3dstackedrram AT chényìwéi highspeedreadcircuitandiodesignfor3dstackedrram AT chenyiwei sānwéiduīdiédiànzǔshìjìyìtǐgāosùdúqǔdiànlùyǔioshèjì AT chényìwéi sānwéiduīdiédiànzǔshìjìyìtǐgāosùdúqǔdiànlùyǔioshèjì
_version_	1719110157541048320

High Speed Read Circuit and I/O Design for 3D Stacked RRAM

Similar Items