A direct sampling boradband radar system in CMOS technology

• Main Authors: Lai, Chang-Ming, 賴昶銘
• Other Authors: Huang, Po-Chiun
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/09475066367317951639

博士 === 國立清華大學 === 電機工程學系 === 102 === Radar systems are widely used in wireless imaging and sensing applications. Microwave radio is a detecting media that is capable of penetrating non-metallic materials, and radar sensitivity is not degraded even in severe weather conditions. These unique fea- tures make radar complementary to visible light-based detection. Therefore, radar gradually shows its essential rule in biometric, vehicular, and security applications. Though radar has been devel- oped for decades, a highly integrated radar system in CMOS is still rare. In this dissertation, two impulse radar systems are proposed and implemented in CMOS. The first chip demonstrates a scalable direct-sampling broadband radar receiver supporting simultaneous digital multi beam array. The chip contains one transmitter and one direct-sampling receiver, which is capable of range estimation. Multiple chips can coop- eratively function as a radar system for azimuth detection. The receivers can reconstruct the scattered waveform into digital such that digital delay-and-sum can be performed. Amplification, du- plication and summation are executed in digital without distor- tion. Parallel array processing in digital is possible to perform si- multaneous multi beam, which enhances the throughput of radar. The sampling time of the receiver elements must be synchronized and controlled independently. The on-chip digital-to-time convert- ers (DTCs) are triggered by a 10-MHz reference source for synchro- nization. The two-step time generation in DTC provides a 6.25-ps resolution over a 100-ns range which is equivalent to a range reso- lution of 0.94 mm over a 15-m range. The receiver has an RF input 10-dB bandwidth of 12.7 GHz with maximal ENOB of 6.4 bit. The proposed architecture is implemented in 65-nm CMOS technology with silicon area of 1.3 × 1.4 mm2. The power consumption is 76 mW under a supply voltage of 1 V. The second chip presents a broadband impulse radio timed-array radar utilizing a time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the receiver determines the time of arrival (TOA), and a four-element timed array enables beamforming. The different time shifts among the channels at the receiver determine the object’s direction of arrival (DOA). Transmitter channels have different shifts, as well, to en- hance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip DTC provides all the necessary timing with a fine resolution and wide shift range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18-µm standard CMOS technology with a die size of 5.4 × 3.3 mm2 and 5.4 × 5.8 mm2 for the transmitter and the receiver, respectively.