| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === This thesis presents a 2.3 GHz, 500 kHz bandwidth divider-less frequency synthesizer architecture that leverages a recently invented sub-sampling phase-locked loop (SSPLL) and a re-quantized modulator to achieve lower in-band and out-of-band noise. A digital correlation loop (DCL) and dynamic element matching (DEM) are proposed as an efficient method to reduce the non-linearity so that the synthesizer can achieve excellent performance. The synthesizer sub-samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. Because the sub-sampling phase detector (SSPD) has a limited locking range and may lock to any possible integer multiple of reference clock, a frequency-locked loop (FLL) is added to ensure proper operation. The automatic frequency control (AFC) is proposed to extend the operated range of VCO by capacitor array controlled. The prototype is implemented in a 0.18-&;micro;m 1P5M CMOS process and its active area occupies 0.75 mm2. Operating under 1.8V, the core parts, excluding the VCO buffer and the input reference frequency buffer, dissipate 9.61mA. Measured phase noise at 2.3GHz achieves -112dBc/Hz and -134dBc/Hz at 50 kHz and 10 MHz, respectively. Integrated phase noise at this carrier frequency yields 266 fs of jitter (measured from 10 kHz to 30 MHz). The figure-of-merit is -239.1dB on the proposed divider-less low-noise fractional-N synthesizer.
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