The Design and Analysis of a Low-Noise Divider-less Fractional-N Synthesizer with Sub-Sampling Phase-Locked Loop Architecture
碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === This thesis presents a 2.3 GHz, 500 kHz bandwidth divider-less frequency synthesizer architecture that leverages a recently invented sub-sampling phase-locked loop (SSPLL) and a re-quantized modulator to achieve lower in-band and out-of-band noise. A digital co...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98456450762713711167 |