Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration

• Main Authors: Chi-Huan Chiang, 蔣季寰
• Other Authors: 劉深淵
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/90227530337968693370

碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === This thesis consists of two parts. The first part implement a digital multiplying delay-locked loop (DMDLL) using switched biasing technique. This DMDLL uses the proposed select logic and its main divider can be turned off to reduce the power consumption. The digitally-controlled oscillator (DCO) uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The integrated RMS jitter is 2.68 ps and the power consumption is 1.51mW at the output frequency of 1050MHz. The second part implements a digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration. It is presented to against the process, voltage, and temperature (PVT) variations. A linearized model of the BBPLL is constructed to analyze the bandwidth of the BBPLL. The proposed bandwidth calibration circuit adopts the adders, the subtractors, and the comparators to replace the area-consuming division circuit, which reduces the area overhead. This BBPLL was fabricated in 40-nm CMOS technology with an active area of 0.0049 mm2. The output frequency is 5 GHz. The integrated RMS jitter is 1.242 ps, and the power consumption is 3.34 mW.