Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration
碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === This thesis consists of two parts. The first part implement a digital multiplying delay-locked loop (DMDLL) using switched biasing technique. This DMDLL uses the proposed select logic and its main divider can be turned off to reduce the power consumption. The...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90227530337968693370 |