Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB

碩士 === 國立臺灣大學 === 電信工程學研究所 === 102 ===

Bibliographic Details
Main Authors:	Chang-Wei Lo, 羅昌瑋
Other Authors:	吳瑞北
Format:	Others
Language:	zh-TW
Published:	2014
Online Access:	http://ndltd.ncl.edu.tw/handle/44119420299021146662

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spelling	ndltd-TW-102NTU054350512016-03-09T04:24:19Z http://ndltd.ncl.edu.tw/handle/44119420299021146662 Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB 兩層印刷電路板上第三代雙倍資料率記憶體系統之信號完整度分析與設計 Chang-Wei Lo 羅昌瑋碩士國立臺灣大學電信工程學研究所 102 吳瑞北 2014 學位論文 ; thesis 116 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電信工程學研究所 === 102 ===
author2	吳瑞北
author_facet	吳瑞北 Chang-Wei Lo 羅昌瑋
author	Chang-Wei Lo 羅昌瑋
spellingShingle	Chang-Wei Lo 羅昌瑋 Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
author_sort	Chang-Wei Lo
title	Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
title_short	Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
title_full	Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
title_fullStr	Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
title_full_unstemmed	Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB
title_sort	analysis and design of signal integrity for ddr3 memory system on two-layer pcb
publishDate	2014
url	http://ndltd.ncl.edu.tw/handle/44119420299021146662
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Analysis and Design of Signal Integrity for DDR3 Memory System on Two-Layer PCB

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