| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === NAND flash memory has been widely utilized in embedded systems and consumer electronics, because of its low-power consumption, high-performance access, non-volatility, and shock resistance. Nowadays, the architecture of SSD is using multiple controllers to handle NAND flash memory chips. Under the architecture of traditional multi-controller design (TMCD), one controller can only take responsibility for the specific NAND flash memory chips on its own bus; nevertheless, under the architecture of parallel multi-controller design (PMCD), any controllers can access any NAND flash memory chips on a SSD. In this thesis, we will propose a method to exploit multi-controller parallelism for solid-state drives regardless of TMCD or PMCD. When a flash translation layer (FTL), which provides a block device interface on top of flash memory, adopts the method, the experimental results show that the FTL for multi-controller design could reduce the total response time up to 5.52%.
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