Flyback PFC Converter with Low-Frequency Voltage Ripple Reduction

• Main Authors: CHI HO LIANG, 梁期合
• Other Authors: Yu-Kang Lo
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/xgh9vy

碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === This thesis studied two circuit topologies to reduce low-frequency output ripple voltage based on flyback power factor corrector (PFC). In the first topology, a reverse ripple voltage is produced by an Inverse-Buck convertor cascode at the output side to cancel the ripple. In the other topology, a bidirectional buck-boost converter is parallel-connected at the output to absorb/ supply power and thus reduce the ripple. Due to ripple reduction, small output capacitance can be used. Therefore, electrolytic capacitor is replaced by solid-state capacitor in the prototype converter to prolong the lifetime. In this thesis, the operating principles and design considerations for the two circuit topologies are analyzed and discussed. 36 V/ 60 W laboratory prototypes are built and tested to verify the theoretical analysis.