Analog IC Design of Modified Offset Min-Sum LDPC Decoder

• Main Authors: Jhih-Peng Lu, 陸志鵬
• Other Authors: 李文達
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/9y4gqh

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 102 === Offset correction methods are often applied to digital decoders for increasing performance, but rare in analog decoders. Thus, based on low-density parity check code, an analog LDPC decoder with current mode is designed in this thesis. Moreover, in order to reduce hardware complexity, an modified offset parameter β is proposed to improve the decoding performance loss caused by simplified Min-Sum algorithm and thus it shows that the offset correction method can be applied to the Min-Sum algorithms and analog decoder chips. Finally, the modified offset min-sum LDPC decoder is implemented using TSMC 0.18μm 1P6M CMOS technology. This chip includes 2562 transistors, supply voltage 1.8V, average decoding throughput 52.8 Mb/s, power consumption 1.26mW. Its’ power speed ratio is 0.024nJ/b and chip area is 0.07mm2 without I/O PAD. Experimental results show that the proposed chip has the characteristics of low power consumption and small area characteristics that is applicable to small handheld products.