Analog IC Design of Modified Offset Min-Sum LDPC Decoder
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 102 === Offset correction methods are often applied to digital decoders for increasing performance, but rare in analog decoders. Thus, based on low-density parity check code, an analog LDPC decoder with current mode is designed in this thesis. Moreover, in order to r...
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ndltd-TW-102TIT056521132019-05-15T21:42:34Z http://ndltd.ncl.edu.tw/handle/9y4gqh Analog IC Design of Modified Offset Min-Sum LDPC Decoder 類比改良補償式最小和低密度同位元校驗碼解碼器晶片設計 Jhih-Peng Lu 陸志鵬 碩士 國立臺北科技大學 電腦與通訊研究所 102 Offset correction methods are often applied to digital decoders for increasing performance, but rare in analog decoders. Thus, based on low-density parity check code, an analog LDPC decoder with current mode is designed in this thesis. Moreover, in order to reduce hardware complexity, an modified offset parameter β is proposed to improve the decoding performance loss caused by simplified Min-Sum algorithm and thus it shows that the offset correction method can be applied to the Min-Sum algorithms and analog decoder chips. Finally, the modified offset min-sum LDPC decoder is implemented using TSMC 0.18μm 1P6M CMOS technology. This chip includes 2562 transistors, supply voltage 1.8V, average decoding throughput 52.8 Mb/s, power consumption 1.26mW. Its’ power speed ratio is 0.024nJ/b and chip area is 0.07mm2 without I/O PAD. Experimental results show that the proposed chip has the characteristics of low power consumption and small area characteristics that is applicable to small handheld products. 李文達 2014 學位論文 ; thesis 61 zh-TW |
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碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 102 === Offset correction methods are often applied to digital decoders for increasing performance, but rare in analog decoders. Thus, based on low-density parity check code, an analog LDPC decoder with current mode is designed in this thesis. Moreover, in order to reduce hardware complexity, an modified offset parameter β is proposed to improve the decoding performance loss caused by simplified Min-Sum algorithm and thus it shows that the offset correction method can be applied to the Min-Sum algorithms and analog decoder chips.
Finally, the modified offset min-sum LDPC decoder is implemented using TSMC 0.18μm 1P6M CMOS technology. This chip includes 2562 transistors, supply voltage 1.8V, average decoding throughput 52.8 Mb/s, power consumption 1.26mW. Its’ power speed ratio is 0.024nJ/b and chip area is 0.07mm2 without I/O PAD. Experimental results show that the proposed chip has the characteristics of low power consumption and small area characteristics that is applicable to small handheld products.
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author2 |
李文達 |
author_facet |
李文達 Jhih-Peng Lu 陸志鵬 |
author |
Jhih-Peng Lu 陸志鵬 |
spellingShingle |
Jhih-Peng Lu 陸志鵬 Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
author_sort |
Jhih-Peng Lu |
title |
Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
title_short |
Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
title_full |
Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
title_fullStr |
Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
title_full_unstemmed |
Analog IC Design of Modified Offset Min-Sum LDPC Decoder |
title_sort |
analog ic design of modified offset min-sum ldpc decoder |
publishDate |
2014 |
url |
http://ndltd.ncl.edu.tw/handle/9y4gqh |
work_keys_str_mv |
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