| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 102 === This thesis presents the research and implement on low noise amplifier for wireless communication system. The chip was fabricated by TSMC commercial 0.18-μm 1P6M CMOS technology. The efficiency of the circuit was demonstrated by measuring at National Chip Implementation Center (CIC). In the design of their operating band 3.1GHz-10.6GHz (UWB) and the three 3-10GHz LNA.
The first UWB LNA, the advantages of using feedback as an input matching transformer to the main structure of the current re-use low-noise amplifier with high gain, low noise and small area. Use spliced use of current recycling infrastructure to achieve current reused to reduce power consumption.
The second UWB LNA, many recent literature, all with the goal to achieve low power consumption, the proposed circuit, the method makes use of body bias transistors to reduce power consumption, and the deep N-well technology can reduce cross-talk through hybrid substrate News. Use RC feedback inputs to match, and then through the spliced (Cascode) architecture to enhance gain and reduce the Miller effect, use the output of the output buffer to achieve a 50 ohm match.
The third UWB LNA, circuit architecture of the gate with the first stage to achieve input impedance matching amplifier section. The second level via spliced (Cascode) architecture and substrate RC technology to enhance gain and reduce the Miller effect, and an increase in the degree of isolation, stability. Use the output of the output buffer to achieve a 50 ohm match.
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