VLSI Design of LDPC Decoding based on Partial Stopping Decoding Algorithm

• Main Authors: Tzu-Hsuan Huang, 黃子軒
• Other Authors: Cheng-Hung Lin
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/14142143998276269480

碩士 === 元智大學 === 電機工程學系 === 102 === With the rapid development in digital communication industrial, the need of transmitting of multimedia and high speed wireless communication is increasing. The error correct code (ECC) has been widely applied to ensure the information can be accepted correctly. Low density parity check (LDPC) codes are proposed in 1962 by Dr. Robert Gallager. Low density parity check codes correct the errors by exchanging information between check node and variable node. The rate of correction in Low density parity check nodes can be improved by increase the number of iteration, however, the power consumption is also increased at the same time. In the process of iteration, check node and variable node update the information and access the memory frequently. So far, a large number of papers has been investigating into decreasing the number of iteration to get the power consumption. However the energy cost in dealing iterations would not be cut down. In this thesis, we propose the partial stopping algorithm. This technique could stop the iterations which already converge. We respectively propose two stopping mechanism: Layer Stopping Criterion and Check Node Stopping Criterion according to Layer Message Processing (LMP) and Two Phase Message Passing (TPMP). In this thesis, the Layer Stopping Criterion and Check Node Stopping Criterion algorithm with the simulations are introduced. In the end, a implementation of a LDPC decoder with Check Node Stopping Criterion is shown.