Hardware Architecture Design of Parallel Multi-Tree Traversals to Provide High Throughput Soft-Output Detection in SDM-MIMO antenna System

• Main Authors: Jia-You Wu, 武珈佑
• Other Authors: Tsung-Hsien Liu
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/7gj4nk

碩士 === 國立中正大學 === 通訊工程研究所 === 103 === In the multiple-input multiple-output (MIMO) systems, the maximum likelihood de- tector (MLD) is the optimal detector. However, MLD requires very high computational complexity; therefore, many suboptimal detectors are developed in order to reduce the computational complexity. Recently, hard-output detecting is a well developed technol- ogy. In order to improve the BER of information, a lot of newly derived researches of soft-output provide back-end decoder with the soft-output information in recent years. It is proposed in this thesis to reduce the tree traversal complexity of the Layered OR- thogonal lattice Detector (LORD) to provide soft-output information in SDM-MIMO system. To improve the implementation design, the studied detector adopts the orthog- onalvaluedecomposition(ORVD)modeltorepresenttheMIMOsystemfromcomplex- valued to real-valued system model. The R-matrix in this model has the paired entries. And to further improve our implementation efficiency of area, we use a table to expand child nosdes on the top layer of tree traversals, and expand only one closest-point child node in remaining layers. For the scenario of four transmit and four receive anten- nas, we expand 36 candidates for 64-QAM signals. Our architecture requires every 6 clock cycles to finish the tree traversal of an input received vector. The designed hard- ware architecture was described by Verilog code, function-verified by Xilinx ISE, and synthesized by Design Compiler. The designed architecture requires 550K gates and provides detection throughput rate 400Mbps with working frequency 100MHz under the TSMC 90 nm CMOS technology.