High-accuracy and Area-efficiency Fixed-width Booth Multiplier
碩士 === 中原大學 === 資訊工程研究所 === 103 === Booth Multipliers are widely used in the design of various kinds of VLSI, while multiplier is the main component of arithmetic logic units(ALU), having a great effect on the area of architecture and instruction cycle.Therefore, it has a significant sense to make a...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54089681859711670562 |
| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 103 === Booth Multipliers are widely used in the design of various kinds of VLSI, while multiplier is the main component of arithmetic logic units(ALU), having a great effect on the area of architecture and instruction cycle.Therefore, it has a significant sense to make a research of the Booth multiplier and proposes an accurate architecture with lower area and higher speed.This paper developed a dynamic error-compensation circuit for fixed-width Booth multipliers of high accuracy based on probability and computer simulation . the proposed begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed approach is area-effective and power-efficient. This study used the TSMC 0.18-um CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.
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