| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 103 === In this thesis, three novel hardware-oriented block-based content adaptive backlight control (CABC) algorithms are proposed for VLSI implementation. It composed of a novel backlight dimming algorithm to reduce power consumption of the backlight module on LCDs and a feature contrast enhancement algorithm to compensate the distortion. In this thesis, the adaptive backlight dimming algorithm raises three methods which are the new average, new maximum and Gaussian distribution method. To improve the image quality, the proposed algorithm was developed to be block-based rather than frame-based. The VLSI architecture of this design includes a grayscale operator, a block-base module, a brightness analysis module, a clipped point calculator, a brightness comparator, a brightness ratio calculator, a pixel compensator, and the PWM pulse generator. To reduce hardware costs and improve executing performance, the three table of the 8-bit to 16-bit square computer, the compensation gain factor and the backlight dimming factor were realized by a looking-up-table technique to replace the high-complexity multiple-square-calculators and dividers. The grayscale module was simplified by replacing the multipliers with adders and shifters to further reducing hardware costs. This design was synthesized by a 0.18-μm technology. The new average, new maximum and Gaussian distribution method contain 18.87K, 19.2K and 20.21K gate counts respectively and which are the new average, new maximum and Gaussian distribution methods the three tables of the its core areas are separately
528,099 μm2, 609,960 μm2 and 630,113 μm2, when operating at 100-MHz. Compared with previous designs, this work improved three methods of the average PSNR values by over 35.51 dB, 42.78 dB and 45.42 dB and reduced LCD backlight power consumption by 46.24%, 50.78% and 48.32%.
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