| Summary: | 碩士 === 逢甲大學 === 資訊工程學系 === 103 === Residue Number System improves the delay of operation. It can be used to solve many problems (e.g., digital signal processor (DSP) [1][2], finite impulse response filter (FIR)[3][4][5] , image and cryptography ).
The conversion process from residue number to binary/decimal number system is very demanding. There are three convert methods. One is Look-up-Table (LUT), another is Mix-Radix-Convert (MRC) [9] and the other is Chinese-Residue-Theorem (CRT)[10][11]. LUT requires lots of memory. But its conversion time is the fastest. Mix-Radix-Convert is a linear operation. So its conversion time is the slowest. MRC hardware cost is the smallest. CRT conversion time is better than MRC, but slower than LUT. We select CRT for converting residue number system to binary/decimal number system in this paper.
Conversion time will be affected for two reasons. One is number of moduli set, the other is the feature of moduli set. The moduli set we select is {2^n – 1, 2^n , 2^n + 1}[12][13]. Because this moduli set reduces computational complexity.
The Altera DE4 supports many devices. It is very suitable to simulate resource-constrained device. We use FPGA on the board to implement and verify the Chinese-Residue-theorem and Residue Number System.
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