Low-Power and All-Digital Reference Clock Generator for WBAN Applications

• Main Authors: Hong, Min-Rong, 洪敏榮
• Other Authors: Sheng, Duo
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/41577033505403768741

碩士 === 輔仁大學 === 電機工程學系碩士班 === 103 === In this thesis, a wide range and a low power digitally controlled oscillator with low output frequency for wireless body area network (WBAN) are presented. The proposed digitally controlled oscillator not only can provide high resolution, but also can generate low frequency clock signal with low power consumption and low circuit complexity as compared with conventional approaches. The proposed design digitally controlled oscillator employs a cascade-stage structure with coarse tuning and fine tuning. The coarse tuning uses the proposed Schmitt Trigger Interlaced to achieve wide range. The fine tuning uses delay cells to generate small delay to achieve high resolution. It can achieve long delay time and low power consumption with low cost. Simulation results show that the operation frequency range is from 6.95MHz to 155.7MHz, and the power consumption can be improved to 79.74µW (@6.96MHz) with 4.6ps resolution in TSMC 0.18µm CMOS process technology. The proposed DCO is integrated into the ADPLL that used resulting of proposed DCO as reference clock to compare frequency with inner DCO to lock. The proposed design of ADPLL with some simple block that can use gate-level or Verilog Hardware Description Language (Verilog HDL) to implement. Thus, the design time and design complexity can be reduced by using Verilog HDL.