High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications
碩士 === 輔仁大學 === 電機工程學系碩士班 === 103 === In this thesis, high conversion rate, conversion wide range and high-resolution time-to-digital converter for positron emission tomography (PET) applications are presented. The proposed TDC not only can achieve high speed of operation, but also have low circ...
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ndltd-TW-103FJU004280222017-03-26T04:24:14Z http://ndltd.ncl.edu.tw/handle/41984075411891849642 High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications 應用於正子斷層掃瞄之高轉換速度與寬轉換範圍時間數位轉換器設計 Jia-Wei,Jian 簡嘉韋 碩士 輔仁大學 電機工程學系碩士班 103 In this thesis, high conversion rate, conversion wide range and high-resolution time-to-digital converter for positron emission tomography (PET) applications are presented. The proposed TDC not only can achieve high speed of operation, but also have low circuit complexity as compared with conventional approaches. This thesis presents two different time-to-digital architectures; the first proposed architecture employs a two-level cascade-stage structure to achieve high timing resolution and wide sampling range at the same time. Simulation results show that the proposed TDC can be improved to 200MHz with 50ps resolution in 90nm CMOS process technology. The second proposed architecture employs multi-level cascade-stage structure with interpolator to improve timing resolution, and achieve low power consumption, Simulation results show that the proposed TDC can be improved to 200MHz with 25ps resolution in 0.18µm CMOS process technology. In addition, the proposed TDC can be implemented with standard cells, making it easily portable to different processes and very suitable for biomedical chip applications. Duo Sheng 盛鐸 2015 學位論文 ; thesis 49 zh-TW |
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碩士 === 輔仁大學 === 電機工程學系碩士班 === 103 === In this thesis, high conversion rate, conversion wide range and high-resolution time-to-digital converter for positron emission tomography (PET) applications are presented. The proposed TDC not only can achieve high speed of operation, but also have low circuit complexity as compared with conventional approaches.
This thesis presents two different time-to-digital architectures; the first proposed architecture employs a two-level cascade-stage structure to achieve high timing resolution and wide sampling range at the same time. Simulation results show that the proposed TDC can be improved to 200MHz with 50ps resolution in 90nm CMOS process technology. The second proposed architecture employs multi-level cascade-stage structure with interpolator to improve timing resolution, and achieve low power consumption, Simulation results show that the proposed TDC can be improved to 200MHz with 25ps resolution in 0.18µm CMOS process technology. In addition, the proposed TDC can be implemented with standard cells, making it easily portable to different processes and very suitable for biomedical chip applications.
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author2 |
Duo Sheng |
author_facet |
Duo Sheng Jia-Wei,Jian 簡嘉韋 |
author |
Jia-Wei,Jian 簡嘉韋 |
spellingShingle |
Jia-Wei,Jian 簡嘉韋 High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
author_sort |
Jia-Wei,Jian |
title |
High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
title_short |
High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
title_full |
High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
title_fullStr |
High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
title_full_unstemmed |
High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications |
title_sort |
high-conversion rate and wide-range time-to-digital converter for pet applications |
publishDate |
2015 |
url |
http://ndltd.ncl.edu.tw/handle/41984075411891849642 |
work_keys_str_mv |
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