| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 103 === In this thesis, utilizing two different architectures of the frequency synthesizer to achieve low phase noise performance and uses the specification of 60 GHz wireless communication systems as design considerations. The paper is divided into three parts to be discussed separately.
The first part describe the basic concepts of phase-locked loop, principles of each sub-circuits, the characteristics of the frequency synthesizer, phase noise analysis of the oscillator, and the relationship between phase noise and phase accuracy of the quadrature oscillator would be expounded. The second part introduces the frequency synthesizer which adopts the low noise harmonic generator and injection-locked tripler is implemented with 90nm CMOS. The frequency tripler provides the tuning range 44.01 GHz to 52.95 GHz and its phase noise is -91.31 dBc/Hz at 1MHz frequency offset. The overall power consumption of the frequency synthesizer is 55mW. The last part discuss the injection-locked frequency synthesizer with quadrature outputs which uses the injection-locked technique to improve phase noise of the frequency synthesizer. The output frequency range of the frequency synthesizer is designed for 42.6 GHz to 51.5 GHz with the phase noise is -94.31 dBc/Hz at 1MHz frequency offset by using the injection-locked technique and power consumption of whole circuit is 61.6mW.
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