| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 103 === In modern IC design flow, powerplanning plays a crucial role in the stage of physical design. Due to advance in manufacture technology, the number of transistors have been increased substantially and the netlists have been more complicated in a chip. Thus, it caused the difficulty in routing stage. It became an important issue considering routability during powerplanning. In most industrial practice, experienced engineers complete the power network through EDA tools manually. In order to satisfy with the constraint of IR-drop, they always use a large amount of metal stripes to cover the whole chip. Such method will cause power network using too many unnecessary areas and routing resources, the cost of the design will increase. Additionally, some power strips will be removed when finding out un-routable regions during routing stage. However, such method may delay design cycle. Nevertheless, most of the previous researches concern about wire sizing to satisfy with the constraint of IR-drop, but few of them mention about routability issue. Unlike these previous works, this thesis adopts an equivalent circuit model to estimate the total usage area of power network to meet the constraint of IR-drop, and use such a suitable width that power stripes take less routing resources. Also, we consider the routing congestion, determine the location of each power stripes based on the dynamic programming algorithm, and make the whole design have good routability. The experimental results validate our method can not only satisfy with the constraint of IR-drop, but also make designs very routable.
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