| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === Modern general-purpose computation on graphics processing units (GPGPUs) explore parallelism in applications by building massively parallel architecture and applying multithreading techniques to hide the instruction and memory latencies. Such architectures become increasingly popular for parallel applications using CUDA/OpenCL programming languages. In this paper, we investigate thread (warp) scheduling algorithms on such highly-threaded GPGPUs. The traditional round-robin scheduling schemes are inefficient in handling instruction execution and memory accesses with disparate latencies. We introduce a memory contention-aware warp scheduler which schedules warps by checking the status of memory unit: it schedules a memory instruction to execute whenever possible if the memory unit is available; if not, it intends to not schedule a memory instruction. This approach maximizes the utilization of the memory unit. Performance evaluations demonstrate that the proposed scheduler improved the execution times of programs from the NVIDIA SDK, the Rodinia benchmark suite, and the Parboil benchmark suite by 12.36%, 2.87%, and 2.77% over the fine-grained round-robin
scheme, respectively.
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