| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === For portable and wearable devices, energy efficiency is an important issue to last the life time of batteries. In modern ICs, more and more on-chip memories are being integrated on a die. It is well known that Static Random Access Memory (SRAM) will dominate not only area but also power, and performance. Therefore,the demand of low voltage and low power SRAM circuit designs with operation frequency of several MHz have increased dramatically. In the thesis, the background knowledge and the definitions of cell stability for SRAM are introduced are first presented. Then the reliability issue of low supply voltage for SRAM is discussed.
Second, dynamic voltage scaling is a common technique to save power consumption. In this thesis, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to reduce power consumption by lowering unselected sub-bank's supply voltage. The proposed SRAM macro is capable of operating in low-voltage regime. In the SRAM macro, we utilize our previous silicon-proved 9T SRAM bitcell[1] which used data-aware Write word-line structure to lower the dynamic power by operating at a lower operation voltage. An 8 kbits SRAM macro is fabricated in 65nm LP CMOS technology. Measurement results shows that the proposed PC-DVS scheme reduces the array power up to 64% at 500kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.
Finally, the two low power design of conventional 6T SRAM macro are described. Traditionally, for speed and area (density) consideration, designers would prefer to use the conventional 6T SRAM bitcell and place more bitcells on a bitline to save area. Using Hierarchical Bit-line structures to transmit the data from local bit-lines to global bit-lines is a common method in SRAM macro. In this thesis, two types of Hierarchical Bit-line schemes is compared in 28nm HPM technology. Simulation results show that the pass-gate Hier-BL with the charge sharing Read scheme can reduce at least 59% power as compare to NAND-gate based Hier-BL. Then the modifications on a low power SRAM macro generated by memory compiler are introduced. Two modifications are applied to the macro, one is to reduce the number of bitcells on each bit-line, and the other one is using current-latched sense amplifiers instead of voltage-latched sense amplifiers. The post-layout simulation results shows the reduction of dynamic power is near 20% at all three corners.
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