40nm 256Kb Low VDDMIN 8T Dual-Port SRAM Design

• Main Authors: Zheng, Ming-Ching, 鄭銘慶
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/n76mmq

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Dual-port static random access memory (DP-SRAM) has been widely used in graphics chip and media processing because of its multiple access behavior. The DP-SRAM can allow computer CPU to draw the image at the same time that video hardware is reading out to screen. Due to the explosion growth of portable devices, low power design that is crucial key to extend the battery life is becoming main stream over the last few years. A simple way to decrease the dynamic power consumption is to lower the supply voltage down. However, DP-SRAM cell suffers disturbance from dummy read operation induced by the other port when two-port access same row simultaneously. Such disturbance is main reason that prevents DP-SRAM cell from lowering supply voltage down. The main objective of this thesis is to eliminate such disturbance to lower supply voltage down. This thesis proposes two novel write-assists (WA4Tx2-4N and WA4Tx2-2P2N) to mitigate the disturbance and improved VDDmin about 100mV. Plus, another read-write-assist (RWA5T) to enhance read-/write-ability and improved VDDmin about 120mV. Besides, two read-assists (XCWLUD and CSBLUD) are designed to stabilize the DP-SRAM cell from data flipping. The die measurement result shows pass rate is improved about 40.6% by XCWLUD and 69.1% by CSBLUD at 0.88V. All of proposed assistance circuit are support for synchronous and asynchronous clock.