Parameters Extraction and Analytical Models for Layout Dependent Effects in DC and HF Characteristics of Nanoscale CMOS Devices

• Main Authors: Lin, Yen-Ying, 林彥穎
• Other Authors: Guo, Jyh-Chyurn
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/d25m58

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this thesis, the impacts of the layout dependent effects on the nanoscale device performances, will be investigated in a variety of the device layouts. In order to achieve the higher maximum oscillation frequency (fMAX) and the lower RF noise, the multi-finger (MF) devices with the simultaneously varied finger width (WF) and finger number (NF), for an effective reduction of gate resistance (Rg), have been widely adopted in the modern RF circuit designs. However, the multi-finger devices with the continuous scaling of WF will suffer the undesired increase of the compressive stress from STI, which leads to the lower effective electrons mobility (ueff) and thereby the lower transconductance (gm). Moreover, the increase of NF will result in the increase of the total gate capacitance (Cgg) due to the poly-finger-end fringing capacitance (Cf(poly-end)). To facilitate a reliable verification of the impact from the STI stress and other layout dependent effects like effective doping concentration on eff, an accurate extraction of the source line resistance (RS), the effective channel width (Weff), and the gate length (Lg) is mandatory to realize accurate eff extraction. The RS can be calculated by our developed distributed transmission line (TML) model, and the results indicate that the larger NF and narrower WF leads to the higher RS due to the narrower and longer source line. Without taking RS into account will lead to underestimate of the extracted eff. As for Lg and Weff, they can be extracted by using our proprietary high precision capacitance method based US patent 8,691,599 B2「Parameter Extraction Method for Semiconductor Device」. To reduce RS and STI transverse stress, there are two new layouts, such as multi-group (MG) and multi-ring (MR) devices, proposed and implemented in this thesis. In addition to eff, the layout dependent threshold voltage (VT) and drain induced barrier lowering (DIBL) have been investigated as well. In our experimental, the single-finger (SF) devices with the largest lateral STI stress reveal much higher VT than all MF devices, and it suggests the retardation of boron diffusion caused by the compressive stress. Regarding DIBL, the experimental results indicate that the narrower WF will bring about the benefit of the suppression of DIBL due to the corner fringing field coupling from the drain to the poly-gate extension. In Chapter 3, a new analytical VT model incorporating 3-D DIBL effect has been developed to predict the WF scaling effects in DIBL. Furthermore, the suppressed boron diffusion may reduce the source/drain extension (SDE) overlap length (LSDE). In Chapter 4, This influence of layout dependent stress on LSDE has be verified and proven by our new method for an accurate extraction of LSDE and RSDE. Finally, in Chapter 5, the layout dependent effects in high frequency characteristics such as the cut-off frequency (fT) and fMAX will be demonstrated and investigated. The abnormal layout dependence revealed in the Rg extracted by the conventional Y-method suggests that the non-negligible parasitic elements like RS and the source inductance (LS) in a 4-terminal (4T) MOSFET should be taken into account. An improved Rg extraction method to be valid for 4T MOSFETs becomes an interesting and challenging work in the future. Regarding fT and fMAX, it is found that the larger NF and smaller WF intended to reduce Rg generally leads to lower fT, due to a significant increase of Cgg, and further impact on fMAX , even if the reduced Rg may improve fMAX in some cases. Thus, the solutions for the optimized device layouts deserve an extensive research efforts in the future.