Low-power digital signal processor for hearing aids

• Main Authors: Chang, Kuo-Chiang, 張國強
• Other Authors: Liu, Chih-Wei
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/09493415517585964868

博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Hearing aids are designed to amplify sound to compensate hearing losses. Modern hearing aids usually apply digital technology to process sound. With the improvement of digital technology, more and more sophisticated hearing loss fitting methods can be realized by advanced digital signal processing to improve quality of the compensation. However, the battery capacity does not grow with the increasing complexity of digital signal processing because of the limited physical dimension of hearing aids. Therefore, modern hearing aids also need to reduce energy consumption to extend the battery life with the improvement of signal processing. This dissertation addresses the advanced digital signal processing design of auditory compensation in both algorithmic and architectural levels. A quasi-ANSI S1.11 filter bank is presented to decompose input signals into 18 1/3-octave frequency bands. The delay of the proposed filter bank is limited under 10-ms constraint, and 93% multiplications are saved by multi-rate structure. A complexity-effective compression algorithm is addressed to squeeze the amplified signals into the reduced dynamic range of hearing losses. By algorithmic and numerical optimization, the proposed compression algorithm reduces 90% complexity. Further 50% complexity is also reduced by implementing a three-channel compression with multi-rate architecture. In order to realize the auditory compensation algorithms, a low-power and programmable computing platform is developed by integrating heterogeneous multiple processing elements. Each processing element consists of a tiny RISC processor and several specific hardwired accelerators. The RISC processor controls the algorithm flow for flexibility and the hardwired accelerators process the computation intensive tasks for energy-efficiency. To implement the platform efficiently, variable-latency design techniques are also presented. The proposed variable-latency design technique by data speculation reduces 44% critical path delay and the hearing aid computing platform can be operated under low voltage with less hardware cost. The overall hearing aid system integrates auditory compensation, noise reduction, and feedback cancellation algorithms with the proposed heterogeneous multiple processing element. The integrated system was fabricated with TSMC 65nm process, and the measured results present the auditory compensation consumes 170 µW while the overall hearing aid system consumes 500 µW under 0.5V and 6 MHz frequency.