Design of the Complementary Face-Tunneling FET for Ultra-low Power Applications

• Main Authors: Zhao, Yu-Bin, 趙堉斌
• Other Authors: Chung, Shao-Shiun
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/tmgd3z

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Tunneling effect is a common phenomenon when transistors shrink to the nanoscale, for transistors, usually considered as negative effects mostly. Tunnel FET is a transistor used tunneling mechanism as the control switch of channel, in recent years, it is considerable potential as a promising candidate for next generation transistor. The reason is that TFET and MOSFET operating mechanisms are not the same, it able to avoid many of the short channel and reliability issues. TFET provides the capability of less than 60 mV/decade subthreshold swing, and a very small leakage current. These characteristics favor scaling of VD, reduce energy consumption, for example, applications in low power device. But TFET still has some issues which need to be overcome, such as low on-state current value, drain inducing barrier lowering (DIBL), asymmetric conductance, and larger gate-to-drain capacitance. The main research direction of this paper is to explore how to effectively improve the current value of TFET, and avoid DIBL off-state leakage that reduced steep transfer characteristics. A new design of face tunneling FETs with a raised drain has been proposed to improve the short channel effect and performance. By tuning important parameters to optimize the device, the electrical characteristic of result as compared with hetero-planar TFET and face TFET, the results showed that the new face tunnel FET structure with heterojunction tunneling mechanisms can effectively improve the on-current and reduce the leakage current. Moreover, for the first time, the body effect of TFETs has been studied by using a body-contacted GeOI wafer. With a forward body bias, TFETs show higher Ion with a penalty of larger Ioff, but suppressed Ion of TFETs has been observed with a reversed-bias one. Next, another critical issue, that is, unexpected large gate-to-drain capacitance, Cgd in TFETs, which certainly hurts the delay of logic circuits. We found our design has well-performed complementary TFETs (CTFETs) with a good scalability and a much lower Cgd. As a result, our TFET inverter can be compatible to MOSFET one. Finally, by using SRAM cell as a benchmark, this newly designed TFET with the body-bias can be successfully operated down to Vdd= 0.2V and shows better noise-margin in comparison to that of conventional CMOS SRAM. These results show good potentials of TFET for the ultra-low power applications.