| Summary: | 碩士 === 國立交通大學 === 電機資訊國際學程 === 103 === In practical Digital IC implementation flow, FPGA prototyping is a very important step. Before the hardware design is signed-off for tape-out, it is essential to verify the functional correctness and performance of the IC/hardware in constrained test environment. FPGAs provide an easy and fast way to verify the hardware design. This thesis proposes a dual mode (SC and HSI) and dual standard wireless baseband receiver which implements the IEEE standards 802.15.3c and 802.11.ad. It has two operation modes, single carrier (SC) and high speed interface (HSI). The single carrier mode receives data on a single carrier while the high speed interface mode is based on orthogonal frequency division multiplexing, OFDM. There are three main blocks of the receiver, the synchronization block, frequency domain equalizer, and phase noise cancellation. All the blocks share the hardware of the SC and HSI modes to reduce the area, complexity and power consumption.
Besides, this thesis discusses not only the FPGA prototyping flow with different methods to translate an ASIC specific RTL design for FPGA implementation but also various methods to upgrade the operation frequency (speed) of the system to achieve target Gb/s speeds on FPGA.
The baseband receiver is implemented on Xilinx VC707 FPGA evaluation board and the receiver works at 95MHz with 8X-parallelism architecture. The output from the baseband receiver is analyzed using ChipscopeTM Pro integrated logic analyzer. The data rates achieved from the prototype are 1.5 Gb/s and 4.5 Gb/s for QPSK and 64QAM data in HSI mode, respectively.
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