| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 103 === With the rapid growth of technology and the trend of integrated circuits, the Phase-Locked Loop (PLL) plays an important role in a variety of integrated circuit applications. The Phase-Locked Loop generates a stable clock signal as a reference signal to ensure circuits operate correctly, so it is indispensable in many applications.
In the early development, PLL design was realized by analog form mainly. However, as the process technology updates continuously, analog circuits need to be redesigned during each change of process. In addition, the passive components of the analog PLL cost lots of area. Therefore, the All-Digital PLL (ADPLL), instead of the analog design, becomes a hot topic around the world in the decade. The advantages of ADPLL are low power consumption, small area, and fast lock time, but it is required to enhance the performance of jitter and phase noise.
In the first chip, a 350-800MHz all-digital phase-locked loop (ADPLL) by Full-Custom form, implemented in 0.18um CMOS process, using multi-stage time-to-digital converter (TDC) is presented. The proposed multi-stage TDC combines the advantage of the general TDC, vernier TDC, and time amplifier. Using each kind of TDC circuit repeatedly and inserting 8x time amplifier achieve high resolution. The TDC shows the minimum resolution of 1ps with a total conversion range of 1ns. The proposed DCO is a linearly periodic structure, and the operation range is from 350MHz to 830MHz
The design of the second chip is based on that of the first chip, and adds the Frequency Tracking Engine (FTE) to reduce the system lock time. The proposed Frequency Tracking Engine utilizes the fastest and slowest frequency of DCO to calculate the gain of DCO (KDCO), and then use the result to ensure the DCO oscillate at the calculated target frequency. After the fast tracking algorithm is completed, the general operation will take over until the system locks.
Both chips are locked at 800MHz. The measurement results of the first chip show 11.67ps peak-to-peak jitter. The ADPLL has an area of 0.068mm2 and the power dissipation of 17.87mW. In the second chip, simulation results show 8.33ps of peak-to-peak jitter, and the power dissipation is 11.54mW.
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