| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 103 === This thesis proposes a 0.5V process variation compensation system. This system provides the microprocessor a rectifiable supply voltage, which can compensate the influence of process variation on the microprocessor. This system consists of two parts: a digital circuit under test (CUT) and a dynamic voltage scaling system. The digital circuit under test is used to model the complication and current consumption of the microprocessor. The dynamic voltage scaling system is realized by a delay-lock loop (DLL). The voltage controlled delay line is used to replicate the critical path of the CUT. The delay time of the critical path is locked in one clock cycle. Finally, the switched capacitor regulator is used to provide the supply voltage to the CUT and the DLL.
This chip is fabricated in TSMC GUTM 90nm CMOS technology. The total silicon area is 0.718 . The supply voltage of this compensation system is 0.5V, and reference frequency is 10MHz. The output range of the switched capacitor regulator is 0.15V~0.45V. When the system operates in TT corner, the output voltage of the switched capacitor regulator is 0.3V. The current consumption of CUT is 100uA, and the power consumption of the overall system is 85.6uW.
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