| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 103 === This thesis presents a design of the clock generator for the application of GALS (Globally-Asynchronous Locally-Synchronous) system. The clock source has the ability of fast-locking and alleviating the impact of output frequency deviation due to temperature variations.
The all-digital frequency-locked loop generates the output frequency of the digitally controlled oscillator as the target frequency first by means of negative feedback. Then the feedback loop was disconnected and the oscillator tuning word was kept so that the oscillator outputs the target frequency at free-running to serve as the clock source that the GALS system needs. By doing so, the clock generator does not need a continuous reference clock. Hence, the reference clock generator can then be shutdown. SoC system can save much of the silicon area and its power, which makes it much more attractive.
Since the open-loop oscillator's output frequency is sensitive to the supply voltage and temperature variations, we propose a temperature compensated circuit design to make it less sensitive to temperature variations.
To achieve fast lock-in, the Regula Falsi method has been used in the design of the all-digital frequency-locked loop. When the output frequency is closed to the expected frequency, the loop switches to a closed loop with a digital filter. Initially, the filter is set to have a wide bandwidth for a faster locking process. After the output frequency is locked to the expected frequency, the filter's bandwidth is set to a smaller one for stable output frequency. Measurement results show that the lock-in process is less than 11 cycles at its worst.
To address the output frequency deviations of the free-running digitally controlled oscillator due to the temperature variations, a constant-gm circuit is used to alleviate the parameter change of the transistors in the delay cells. In particular, the proposed method works under different control voltages.
A test chip has been implemented in TSMC 0.18μm CMOS technology. The core area is 0.239 〖mm〗^2 and the whole-chip area with bonding pads is 0.895 〖mm〗^2. Measurement results show that the chip can operate correctly when the output frequency is between 1.85 GHz and 3.0 GHz. When the output frequency is 2.4 GHz, the lock-in time needs 7 reference cycles. The measured rms jitter is 0.545% unit-interval (U.I.) and the peak-to-peak jitter is 4.334% unit-interval (U.I.). The phase noise spectral density at 1 MHz offset is measured to be -84.09(dBc/Hz). The power consumption of the core circuits is 17.74 mW.
The measured effective temperature coefficient of the free-running digitally controlled oscillator is 186 ppm/℃ in the range between -40℃ and 100℃.
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