| Summary: | 碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 103 === Metal silicides have been developed as interconnect and contact materials for semiconductor device fabrication. CoSi2 is the most widely used material for silicide technology after 180nm, since it has immunity to narrow line width effect, lower resistivity and good thermal stability. However, with the continued scaling down of device features, the stress induced by physical structures has noticeable effect on the formation of CoSi2 in deep sub-micron ULSI technology. During the growth of CoSi2, it has been reported that the main diffusing specie is Co atom for the solid phase reaction and volumetric change. We found the diffusion of Co atoms is also affected by the stress.
The results show as follows. The tensile stress effect of gate spacer film and silicon interface for the formation of CoSi2 physical structures, induced Co atoms diffusion to under gate spacer. The Co atoms diffusion induced under gate spacer void、the drain-to-source junction leakage current and short-channel effects problem. In this thesis, the formation of CoSi2 affected by product physical structures induced problem has been studied in detail.
The used different process parameters condition of cobalt silicide formation process of this studied. Example RAT1 Anneal process time(30s、60s、90s)、RAT2 anneal process temperature (650℃+725℃、725℃、740℃)/ RAT2 anneal process time (60s+30s、60s、30s) and Co Sputtering deposition thickness(115A、90A、95A、135A)/ Co Sputtering process temperature(100℃、300℃) then the wafer samples to do electrical characteristic measurement、cross-sectional TEM and EDX analysis . The results show as follows. The tensile stress effect induced Co diffusion to under gate spacer. The Co Sputtering deposition process temperature can effectively improvement, the current encountered problems also can be solved of product.
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