The Design of A Linearized CMOS Power Amplifier in Front-end Circuits for Dedicated Short-range Communication Systems

• Main Authors: Guan-Lin Guo, 郭冠麟
• Other Authors: Ro-Min Weng
• Format: Others
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/24366478018434309877

碩士 === 國立東華大學 === 電機工程學系 === 103 === This thesis is focused on the research of the RF CMOS power amplifier for dedicated short-range communication (DSRC) systems. Two circuits are proposed. one is a high linearity power amplifier. The other is a gain reused amplifier for front-ends in RF transceivers. These two circuits are designed and manufactured by using tsmc 0.18μm CMOS process. A linear power amplifier is presented as a small input power and high gain circuit. Therefore it can be used for low power system which high output power is required. Three methods are used to improve linearity and to increase efficiency. A derivative superposition (DS) method which is different from tradition DS method at the final stage is used to reduce third harmonic term and to increase the first harmonic term. A method is presented to assist circuit design apart from load pull and load line methods. A nonlinear graphic derivation method is adapted to improve nonlinearity within stages. An extend efficiency equation derivation is also added. The last gate efficiency and total power decide the total efficiency when high gain and small input power are required. The proposed power amplifier is a class AB type amplifier and is operated at 5.4~6.1GHz. The output specification corresponds to class B power. At 5.8GHz only -13dBm is needed to achieve OP1dB to 13.3dBm output power. The maximum power added efficiency is 37%. A gain-reused architecture is presented for front-ends in RF transceivers which is different from traditional bi-directional ones. It is designed by altering T/R switch signal path. Power amplifiers in transmitting oath can reuse the gain provided by low noise amplifiers in receiver path. Circuits are proposed to reduce insertion loss and to keep efficiency with a small input power. Also the reused architecture has an advantage of compact area. That architecture controls two T/R switches for LNA and PA. Three bias circuits are added to control on/off in transmitter or receiver. That amplifier path used the second and the third methods to increase both efficiency and linearity. Switches are design with body-floating technique to improve isolation and insertion loss. The transmitter type also is operated in class AB at 5.5~6.25 GHz. The output specification corresponds to class B power amplifier. At 5.9GHz only -13dBm is needed to obtain OP1dB to 13.3dBm output power. The maximum power added efficiency is 19%. While operated in 5.4~6.1 GHz as receivers with a small gain about 15dB and noise figure about 5.2dB. In receiver mode, the power dissipation is 14mW. While in transmitter mode, the power dissipation is 112mW.