| Summary: | 碩士 === 國立高雄海洋科技大學 === 微電子工程研究所 === 103 === It is well known that to achieve higher resolution for the delta-sigma modulator one would need to either raise sampling frequency or use higher order modulator instead. As design complexity increases the power consumption as well as overall chip area and cost would increase. For a given product specs, how to achieve the optimal design with the minimum power consumption and area will be the focus of this thesis.
Using the TSMC 0.18 μm technology, both the first-order and the second-order delta-sigma modulators were designed and analyzed. It was found that by using a single-loop topology with a full differential-in/differential-out integrator (the OTA has designed gain > 70dB, phase margin > 60 °, unity bandwidth > 100 MHz and common mode rejection ratio > 60 dB at room temperature,) Matlab and HSPICE simulated results show that for the first order modulator with a sampling frequency = 10.24 MHz (oversampling ratio, OSR = 256,) input signal = ±0.2 V, signal frequency = 20kHz, the achievable SNDR = 55 dB, equivalent to 8.5 effective number of bits for a total power consumption = 1.6 mW. For the second order modulator with the same sampling frequency and oversampling ratio, input signal = ±0.3 V, the achievable SNDR = 78 dB, equivalent to 12.5 effective number of bits for a total power consumption = 1.13 mW. Both chips were taped out and fabricated by the TSMC.
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