VLSI Implementation of Modified Set Partitioning in Hierarchical Trees Algorithm for ECG Compression Systems

• Main Authors: Xaio-Yi Lin, 林孝頤
• Other Authors: Jui-Hung Hsieh
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/74326313514311482290

碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 103 === Transform-domain compression algorithms have been refined through years of practice. Existing experiments indicate that discrete wavelet transform (DWT) has better compression ratio. Data compression algorithm based on DWT has been adopted in 1-D ECG data compression in recent years, and gains outstanding efficiency. One critical feature of DWT is that the conversion coefficients in lower band tend to have larger absolute value. Such feature fits Set Partitioning In Hierarchical Trees (SPIHT) algorithm as the coding method. However, traditional SPIHT coding algorithm adopts list searching method, which needs enormous memory. Furthermore, the duration of searching individual node in hierarchical tree is time-consuming, so it is not appropriate for hardware implementation. In order to overcome these difficulties, MSPIHT coding algorithm has been proclaimed. The algorithm adopts bit-plane as its input format, replaces list in traditional SPIHT algorithm with flag array, and integrates the three lists to build a check bit mechanism. These progresses lower the searching duration for successive coefficients in coding process. The MSPIHT coding algorithm is relatively modular and regular, and further makes the coding process faster and stable. This thesis performs MSPIHT under VLSI model, verifies Verilog language under Synopsys VCS, and uses Synopsys Design Compiler to conduct logic synthesis with SAED 90nm. The result shows that the coding time of the 15-minute ECG data, provided by Massachusetts Institute of Technology, can be lowered to 0.4 seconds with the MSPIHT hardware model of this thesis. It realizes real-time coding, and it can be reconstructed perfectly.