The Circuit Implementation and Design Considerations of CMOS Imagers for Wide Dynamic Range and 3D-Integrated CMOS Image Sensor

• Main Authors: Yeh, Shang-Fu, 葉尚府
• Other Authors: Hsieh, Chih-Cheng
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/06710895250758445877

博士 === 國立清華大學 === 電機工程學系 === 103 === The fast growing demand of thin and compact mobile and wearable devices has driven the efforts to reduce the size of camera module. CMOS image sensor (CIS) with small pixel dimension is an effective solution to implement a small size camera module. The design challenges of CMOS image sensor with small pixel dimension are low dynamic range, low full well capacity (FWC) and low sensitivity. In this thesis, three new techniques are proposed to address the problems. Firstly, a dual-exposure single-capture wide dynamic range CMOS image sensor for mobile devices is proposed. The proposed sensor achieves column-wise highly/lowly-illuminated pixel detection, and only the “adequate” voltage signal (long- or short-exposure signal) is digitized. With an integrated highly/lowly-illuminated pixel detection function in the column-wise single slope ADC, each pixel is read out only once with highly- or lowly-illuminated pixel index for synthesis of a wide DR frame. This approach can dramatically reduce the power dissipation compared to existing multi-frame-readout solutions. The dynamic range expansion ratio is programmable, and depends on the time ratio of long-exposure to short-exposure period. Secondly, a novel single-slope ADC design and operation is proposed to expand full well capacity of CMOS image sensor with small pixel dimension. With the proposed technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared to the general double A/D conversion operation. Finally, because 3D IC is an emerging solution to reduce chip size, a 3D-integrated IV CMOS image sensor layer with built-in self-test function for 3-layer stacking CMOS imager is proposed. A modular CIS sub-array is proposed with new readout and control scheme. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. The proposed 3D-integrated CIS layer is very suitable for small size camera module applications.