| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 103 === Recently, mobile and intelligent electronic devices have spread everywhere, but this has brought new issues to system design. We have to achieve low power and high system performance in a battery-limited condition. The conventional 2-MACRO architecture can reach the performance demand with a low cost; but for systems with limited battery-power, the 2-MACRO architecture may consume large power and time to store the data. The single-MACRO architecture has been developed to solve this issue.
Emerging non-volatile memory devices have low-power, high speed and are compatible with logic processes. Due to these merits, we have proposed a new 5T2R non-volatile ternary content addressable memory cell (5T2R nvTCAM cell) using this device. Replacing SRAM cell with a ReRAM device has greatly decreased the layout area of TCAM cell. Since there is zero leakage current in stand-by mode, the power consumption is further decreased. The proposed 5T2R nvTCAM cell reads the data stored in the ReRAM with a small current, and then decides whether the match-line needs to be discharged according to the compared result. Compared with previous works, the proposed 5T2R nvTCAM cell has improved the search speed and tolerable resistance ratio.
In summary, we have proposed a 5T2R nvTCAM cell design. Its access time is 1.6ns with a supply of 1V VDD. It can successfully perform search operation under a wide range of resistance ratios, and maintain a fair
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search speed under different conditions. The special L-shaped cell layout can accomplish a high density nvTCAM cell array
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