| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 103 === Embedded DRAMs are widely used in many electronic products due to its more cost-effective than SRAM and its faster read/write random access than FLASH. However, increasingly large power consumption is a big problem in SOC system. For this reason, low power design issue should be taken into consideration. For embedded DRAM, the stored data should be confirmed to retain in cell array with conventional period in self-refresh mode. But operating at low voltage, the cell data retention time will eliminate much shorter than that in higher voltage condition. Hence, there is quick refresh and generates an additional AC component of data retention power at low voltage with conventional period.
To solve this problem, we propose a low voltage sensing and write-back control scheme to extend data retention time in lower voltage condition. By operating in write-back phase, it increase potential of data so that margin enhancement in sensing phase achieves to read out data correctly in low voltage mode, and reduces power consumption in self-refresh mode.
A low voltage sensing and write-back scheme is implemented in a 4Kb embedded DRAM macro, which is fabricated in TSMC 65nm Generic CMOS process. The measurement results show that, 57% reduction of data retention power in low voltage can achieve at room temperature.
|
|---|
