The Design of a High Efficiency/Synchronous CMOS/Voltage Mode/Dual Control DC to DC Switching Regulator

• Main Authors: Po-Chia Huang, 黃柏嘉
• Other Authors: Jia-Chuan Lin
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/07428244124574969269

碩士 === 國立臺北大學 === 電機工程學系 === 103 === Due to the popularity of smart phones, the preferred considerations of power requirement for mobile devices are efficiency and process area on chip. This paper presents a high efficiency dual mode control of the DC-to-DC buck switching regulator / converter, and the operating range is 3.3V to 5V (input voltage range) transfer to Vin to 1.8V (output voltage range). The converter operates at switching frequency of less than 500k Hz, the load range is 3mA to 500mA, the conversion efficiency is more than 88% in each load, the output ripple voltage is within 20mV in heavy load for each input supply voltage (3.3V~5V). The proposed converter chip was fabricated by “TSMC 0.35um Mixed-Signal 2P4M Polycide Process” provided by National Chip Implementation Center. The area of chip is 1.7619×1.88mm2. When the output is in light load, the converter will switch to PFM mode in this moment. It can reduce frequency to reduce the switching loss. And effectively shut down another feedback path. The maximum light load conversion efficiency is 97%. In addition, this work used inductor current and error signal to make the PFM function. This converter adds a soft-start circuit to limit over shoot current and over shoot voltage in the start-up.