| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells to construct the desired programmable delay line. Compared to previous works, our method is 5 to 25 times more efficient in resource usage. However, it costs too much time to measure all delay values. To save time, we only measure partial delay values and use the proposed generation program to predict all delay values. Then, using the proposed selection program to select the desired delay values. To automatically measure delay values, we develop the LabVIEW program which can control the PXI FPGA Carrier and the oscilloscope at the same time. The measurement results show that the proposed programmable delay line achieves 50 ps resolution with 11.1 ns dynamic range. The power consumption is 1 mW.
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